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CXP828P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP828P60 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, fluorescent display panel controller/driver, remote control reception circuit, and PWM output circuit besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. The CXP828P60 also provides sleep/stop function that enables lower power consumption. CXP828P60 is the PROM-incorporated version of the CXP82860 with bult-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 122s at 32kHz operation * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 1536 bytes (including fluorescent display area) * Peripheral functions -- A/D converter 8 bist, 8 channels, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronized type, 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32kHz timer/counter -- Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel. High voltage drive output port of 56 pins (40V) Maximum of 640 segments display possible Display timing number of 1 to 20 Dimmer function Incorporated pull-down resistor Hardware key scan function (Maximum of 16 x 8 key matrix supportable) -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO -- PWM output 14 bits, 1 channel * Interruption 16 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95Z36-ST
Block Diagram
AVSS
AVREF
INT0 INT1 INT2 INT3/NMI
2
G0/A0 to G15/A15 RAM
16
SPC 700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
A16 to A23
8
PORT A
AN0 to AN7
8
A/D CONVERTER
TEX TX EXTAL XTAL RST VDD VSS
8
PA0 to PA7
A24 to A55 VFDP KR0 to KR7 PROM 60K BYTES RAM 1536 BYTES
8
KEY SCAN
PORT B
32
FDP CONTROLLER/ DRIVER
8
PB0 to PB7
PWM
14 BIT PWM GENERATOR
PORT C
8
PC0 to PC7
PORT D
CS0 SI0 SO0 SCK0 FIFO PRESCALER/ TIME BASE TIMER 2
SERIAL INTERFACE UNIT 0
PORT E
SI1 SO1 SCK1
EC0
8 BIT TIMER/COUNTER 0
PORT F
ADJ
2
PORT H
TO CINT EC1 2
16 BIT CAPTURE TIMER/COUNTER 2
PORT G
-2-
FIFO
RMC
REMOCON
INTERRUPT CONTROLLER
8
PD0 to PD7
6 2
PE0 to PE5 PE6 to PE7
SERIAL INTERFACE UNIT 1
32KHz TIMER/COUNTER
8
PF0 to PF7
8 BIT TIMER 1
8
PG0 to PG7
8
PH0 to PH7
CXP828P60
CXP828P60
Pin Assignment (Top View)
G10/A10 G11/A11 G12/A12 G13/A13 G14/A14 G15/A15
G2/A2
G3/A3
G4/A4
G5/A5
G6/A6
G7/A7
G8/A8
G9/A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 G1/A1 G0/A0 Vpp PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5 PE6/PWM PE7/TO/ADJ PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 AVREF PA0/AN0 PA1/AN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A21 A22 A23 PH7/A24 PH6/A25 PH5/A26 PH4/A27 PH3/A28 PH2/A29 PH1/A30 PH0/A31 PG7/A32 PG6/A33 PG5/A34 PG4/A35 PG3/A36 PG2/A37 PG1/A38 PG0/A39 PF7/A40 PF6/A41 PF5/A42 PF4/A43 PF3/A44 PF2/A45 PF1/A46 PF0/A47 PD7/A48 PD6/A49 PD5/A50
VDD
A16
A17
A18
A19 PD3/A52
Note) Vpp (Pin 3) must be connected to VDD.
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
-3-
PD0/A55
PD1/A54
PD2/A53
PD4/A51
EXTAL
XTAL
AVSS
VFDP
TEX
RST
VDD
Vss
TX
A20
CXP828P60
Pin Description Pin code I/O Functions (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8pins)
PA0/AN0 to PA7/AN7
I/O/ Analog input
Analog inputs to A/D converter. (8 pins)
PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit output port. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins)
Capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
PC0/KR0 to PC7/KR7
I/O/Input
Serves as key return inputs when operating key scan with fluorescent display panel (FDP) segment signal. (8 pins)
PD0/A55 to PD7/A48 PE0/INT0/ EC0 PE1/INT1/ EC1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5 PE6/PWM PE7/TO/ADJ PF0/A47 to PF7/A40
Output/Output
FDP segment signal (anode connection) outputs. External event inputs for timer/counter. (2 pins)
Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Input Output/Output Output/Output/ Output (Port F) 8-bit output port. (8pins) (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Inputs for external interruption request. (4 pins)
Non-maskable interruption request input.
Remote control reception circuit input.
14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, and 32kHz oscillation frequency division. FDP segment signal (anode connection) outputs.
Output/Output
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CXP828P60
Pin code PG0/A39 to PG7/A32 PH0/A31 to PH7/A24 A16 to A23 G0/A0 to G15/A15 VFDP EXTAL XTAL TEX TX RST AVREF AVSS VDD Vpp VSS Input
I/O Output/Output (Port G) 8-bit output port. (8 pins) (Port H) 8-bit output port. (8 pins)
Functions FDP segment signal (anode connection) outputs. FDP segment signal (anode connection) outputs. (8 pins)
Output/Output
Output
FDP segment signal (anode connection) outputs. (8 pins) Outputs for FDP timing signals (grid connection)/segment signals (anode connection). (16 pins) FDP voltage supply for incorporated pull-down (PD) resistor. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event input, input to TEX, and open TX. Low-level active, system reset. Reference voltage input for A/D converter. A/D converter GND. VCC supply. Vcc supply for incorporated PROM writing. Connect to VDD during normal operation. GND.
Output/Output
Output Input Output Input Input
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CXP828P60
I/O Circuit Format for Pins Pin Port A
Pull-up resistor "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset Input multiplexer A/D converter
8 pins Port B
Pull-up transistor approx. 100k
Pull-up resistor "0" when reset Port B data
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B direction "0" when reset
IP Schmitt input
Hi-Z
RD (Port B) CINT CS0 SI0 SI1 Pull-up transistor approx. 100k
4 pins Port B
Pull-up resistor "0" when reset SCK OUT Serial clock output enable
PB2/SCK0 PB5/SCK1
Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Schmitt input IP
Hi-Z
2 pins
SCK in
Pull-up transistor approx. 100k
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CXP828P60
Pin Port B
Pull-up resistor "0" when reset SO Serial data output enable Port B output selection
Circuit format
When reset
PB4/SO0 PB7/SO1
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) IP
Hi-Z
2 pins Port C
Pull-up resistor "0" when reset
Pull-up transistor approx. 100k
2
PC0/KR0 to PC7/KR7
Port C data
Port C direction "0" when reset Data bus RD (Port C) Key input signal
1 IP
Hi-Z
8 pins Port E PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC
1 Large current 12mA 2 Pull-up transistor approx. 100k
Schmitt input IP
EC0/INT0 EC1/INT1 INT2 INT3/NMI RMC Data bus RD (Port E)
Hi-Z
5 pins PE5 1 pin Port E
IP RD (Port E) Data bus
Hi-Z
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CXP828P60
Pin Port E
PWM Port E output selection "0" when reset
Circuit format
When reset
PE6/PWM
Port E data "1" when reset Data bus Output enable
High level
1 pin Port E
RD (Port E)
Internal reset signal Port E data TO "1" when reset ADJ16K1 ADJ2K1 00 01 10 11 MPX 2
PE7/TO/ADJ
Port E output selection (upper) Port E output selection (lower) "00" when reset TO output enable 1 ADJ signal is a frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2K can be used for buzzer output. 2 Pull-up transistor approx. 150k
High level (with approx. 150k resistor when reset)
1 pin PD0/A55 to PD7/A48 PF0/A47 to PF7/A40 PG0/A39 to PG7/A32 PH0/A31 to PH7/A24 32 pins Port D Port F
Segment output data
Port G Port H
Output selection control signal ("0" when reset)
Port D, F, G and H data "0" when reset
Hi-Z or Low level (when PD resistor is connected)
Data bus RD (Port D, F, G and H) High voltage drive transistor
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CXP828P60
Pin
Circuit format
When reset
Segment output data
A16 to A23
Output selection control signal ("0" when reset) Pull-down resistor VFDP High voltage drive transistor
Hi-Z or Low level (when PD resistor is connected)
8 pins
Segment output data Timing output data
G0/A0 to G15/A15
Output selection control signal ("0" when reset) Pull-down resistor VFDP High voltage drive transistor
Hi-Z or Low level (when PD resistor is connected)
16 pins
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed and XTAL becomes High level during stop.
Oscillation
XTAL
2 pins
TEX TX
* Diagram shows circuit composition during oscillation. TEX IP IP * When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX becomes Low level and TX becomes High level.
Oscillation
TX
2 pins
Pull-up resistor
RST Low level
IP
1 pin
Schmitt input
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CXP828P60
Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVss A/D converter GND voltage A/D converter reference voltage FDP display supply voltage Input voltage Output voltage Display output voltage AVSS AVREF VFDP VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL IOLC Rating -0.3 to +7.0 -0.3 to +13.0 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +7.01 -402 to +7.01 -0.3 to +7.01 -0.3 to +7.01 -402 to +7.01 -5 -15 -50 -30 -120 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V V V V V V mA mA mA mA mA mA mA mA C C mW Incorporated PROM
(Vss = 0V reference) Remarks
All pins excluding display outputs3 (value per pin) Display outputs A20 to A55 (value per pin) Display outputs G0/A0 to G15/A15, and A16 to A19 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port (value per pin) Large current port (value per pin)4 Total for all output pins
Low level total output current IOL Operating temperature Storage temperature Topr Tstg
Allowable power dissipation PD 1) 2) 3) 4)
VIN, VOUT, VOD and AVREF must not exceed VDD + 0.3V. VFDP and VOD must not exceed VDD - 40V. Specifies output current of general-purpose I/O ports. The large current drive transistor is the N-CH transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
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CXP828P60
Recommended Operating Conditions Item Symbol Min. 4.5 Max. 5.5 Unit V
(Vss = 0V reference) Remarks Guaranteed operation range during high-speed mode (1/2, 1/4 frequency dividing clock) Guaranteed operation range during low-speed mode or SLEEP mode (1/16 frequency dividing clock) Guaranteed operation range with TEX clock Guaranteed data hold range during STOP 1 Hysteresis input2 EXTAL3 1 Hysteresis input2 EXTAL3
Supply voltage
VDD
3.5
5.5
V
2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD
5.5 5.5 VDD VDD
V V V V V V V V C
VDD - 0.4 VDD + 0.3 0 0 -0.3 -10 0.3VDD 0.2VDD 0.4 +75
1) Value for each pin of normal input port (PA, PB4, PB7, PC). 2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC. 3) Specifies only during external clock input.
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CXP828P60
Electrical Characteristics DC Characteristics Item High level output current Low level output current Symbol VOH Pins Conditions VDD = 4.5V, IOH = -0.5mA PA, PB, PC, VDD = 4.5V, IOH = -1.2mA PE6, PE7 VDD = 4.5V, IOL = 1.8mA VOL PC IIHE IILE IIHT Input current IILT IILR IIL EXTAL VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V TEX RST PA to PC1 A20 to A55 Display output IOH current Open drain output leakage current (P-CH Tr off state) Pull-down resistance I/O leakage current G0/A0 to G15/A15 A16 to A19 G0/A0 to G15/A15 A16 to A55 G0/A0 to G15/A15 A16 to A55 PA to PC1 PE0 to PE5 RST VDD = 4.5V VOH = VDD -2.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -10 to +75C, VSS = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 -50 -3.3 -8 -30 Typ. Max. Unit V V V V V A A A A A A A mA mA
ILOL
VDD = 5.5V VOL = VDD -35V VFDP = VDD -35V VDD = 5V VOD -VFDP = 30V VDD = 5.5V VI = 0, 5.5V
-20
A
RL
60
100
270
k
IIZ
10
A
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CXP828P60
Item
Symbol IDD1
Pins
Conditions High-speed mode operation (1/2 frequency dividing clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF)
Min.
Typ.
Max.
Unit
22
50
mA
IDD2 Power supply current2 VDD
VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF)
STOP mode VDD = 5.5V, termination of 10MHz and 32kHz oscillation
45
130
A
IDDS1
2.3
10
mA
IDDS2
11
30
A
IDDS3 PA to AC, PE0 to 5, XTAL, EXTAL, TEX, RST
30
A
Input capacity
CIN
Clock 1MHz 0V for all pins excluding measured pins
10
20
pF
1) PA to PC pins specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 2) When all pins are open.
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CXP828P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input pulse width Event count input rise time, fall time 1) Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC0, EC1 EC0, EC1 TEX TX TEX TEX
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 20 Min. 1 37.5 Typ. Max. 10 Unit MHz ns 200 ns ns ms
tXL tXH tCR tCF tEH tEL tER tEF
fC
tsys + 501
32.768
kHz
tTL tTH tTR tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEH). tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
TEX EC0 EC1
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CXP828P60
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input set-up time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
SCK0
tsys + 100
8000/fc-50 100 200
SI0
SI0
tsys + 200
100
SO0
tsys + 200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (CLC: 00FEH). tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
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CXP828P60
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP828P60
Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level width SI1 input set-up time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Ouput mode SCK1 Input mode Ouput mode SI1 SCK1 input mode SCK1 ouput mode SI1 SCK1 input mode SCK1 ouput mode SO1 SCK1 input mode SCK1 ouput mode Min. 1000 16000/fc 400 8000/fc-50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP828P60
(3) A/D converter characteristics (Ta = -10 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage VZT1 VFT2 Ta = 25C VDD = AVREF = 5.0V VSS = AVSS = 0V -50 4910 160/fADC3 12/fADC3 AVREF
AN0 to AN7
Symbol
Pin
Condition
Min.
Typ.
Max. 8 3
Unit Bits LSB mV mV s s
10 4970
70 5030
tCONV tSAMP
VREF VIAN IREF
VDD - 0.5 0 Operation mode 0.6
VDD AVREF 1.0 10
V V mA A
AVREF current IREFS
AVREF
SLEEP mode STOP mode 32kHz operation mode
Fig. 6. Definition of A/D converter terms
FFH FEH
Linearity error 01H 00H VZT Analog input VFT
1) VZT: Value at which the digital transfer value changes from 00H to 01H and vice versa. 2) VFT: Value at which the digital transfer value changes from FEH to FFH and vice versa. 3) fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEH). CKS PCK1, PCK0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16) 0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
Digital conversion value
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CXP828P60
(4) Interruption, reset input Item External interruption High, Low level width Reset input Low level width
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 NMI/INT3 RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
Fig. 7. Interruption input timing
tIH tIL
0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI specifies only for the falling edge) 0.2VDD tIL tIH
Fig. 8. RST input timing
tRSL
RST 0.2VDD
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CXP828P60
Appendix Fig. 9. Recommended oscillation circuit
(i) Main clock (ii) Main clock (iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2 C1 C2
C1
C2
Manufacturer
Model CSA4.19MG CSA8.00MTZ
fc (MHz) 4.19 8.00 10.00
C1 (pF)
C2 (pF)
Rd ()
Circuit example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW
4.19 8.00 10.00 4.19
RIVER ELETEC CO., LTD
HC-49/U03
8.00 10.00 4.19
12
12
0 (i)
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
27 20 50
27 0 20 22 1M (iii)
P3
32.768kHz
Models marked with an asterisk () have the built-in ground capacitance (C1, C2).
Mask option table Product Option item Mask product CXP82832 CXP82840 CXP82852 CXP82860 Package ROM capacitance Reset pull-up resistance High voltage drive pin pull-down resister 80-pin plasitc QFP 32K bytes 40K bytes 52K bytes 60K bytes Existent/Non-existent PROM version CXP828P60Q-180-pin plasitc QFP PROM 60K bytes Existent Non-existent (PD7/A24 to PD0/A55) Existent (G0/A0 to A23)
Existent/Non-existent
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CXP828P60
Characteristics Curve
IDD vs. VDD
(fc = 10MHz, Ta = 25C, Typical) 20.0 10.0 5.0 1/16 dividing mode 1/2 dividing mode 1/4 dividing mode 20
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode
IDD - Supply current [mA]
IDD - Supply current [mA]
SLEEP mode 1.0 0.5 32kHz mode (instruction) 0.1 (100A) 0.05 (50A) 32kHz SLEEP mode 0.01 (10A) 2 3 4 5 6 7
15
1/4 dividing mode 10
5 1/16 dividing mode SLEEP mode 0 5 10 fc - System clock [MHz] 15
VDD - Supply voltage [V]
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CXP828P60
Package Outline
Unit : mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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